Reading your register settings under Linux:

Reading your register settings under Linux:

Register values for the 440BX PCIset are listed in the 440BX Specification in section 3.3. 3.3.24 lists the values for tCL, tRCD and tRP. A 16 bit address under control register 0 (Device 0), at address offset 76h­77h defines these values. The default value is 00h. The three least significant bits are defined such that:

Bit 0:
SDRAM RAS# Precharge (tRP). This bit controls the number of DCLKs for RAS# Precharge.
0 = 3 clocks of RAS# Precharge.
1 = 2 clocks of RAS# Precharge.

Bit 1:
SDRAM RAS# to CAS# Delay (tRCD). This bit controls the number of DCLKs from a Row Activate command to a read or write command.
0 = 3 clocks will be inserted between a row activate command and either a read or write command.
1 = 2 clocks will be inserted between a row activate and either a read or write command.

Bit 2:
CAS# Latency (CL). This bit controls the number of CLKs between when a read command is sampled by the SDRAMs and when the 82443BX samples read data from the SDRAMs. If a given row is populated with a registered SDRAM DIMM, an extra clock is inserted between the read command the when the 82443BX samples read data. For a registered DIMM with CL=2, this bit should be set to 1.
0 = 3 DCLK CAS# latency.
1 = 2 DCLK CAS# latency.

If you wish to read the values of these bits you can download and run 440bx.c. Compile 440bx.c with "gcc -O -c timing timing.c." The program will dump the bit values of address offset 76h of device 0. For example, a board set to 3-2-2 would read something like:

*** 440BX SDRAM Memory Timing ***

CAS# Latency: 3 DCLKs
RAS# to CAS# Delay: 2 DCLKs
RAS# Precharge: 2 DCLKs

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