The operation of SDRAM in relation to latency:

The operation of SDRAM in relation to latency:

We have already covered topics relating to refresh and latency above. We have defined the RAS Cycle (tRC), the RAS Precharge Cycle (tRP), tRAS, AUTO REFRESH and AUTO PRECHARGE as well as the impact of continuous reads or writes versus short reads and writes on these parameters. Now we can look more closely at the process of activating a bank and reading or writing data to that bank.

As discussed previously, commands and data addresses control access to banks of data. Commands are issued by holding the voltage low or high across several leads. Four very important leads are CS#, RAS#, CAS# and WE#. When CS# is high the other three leads are ignored. When CS# is held low the voltages across RAS#, CAS# and WE# determine a set of commands used to manipulate the bank in question.

Commands issued for values of RAS#, CAS# and WE# when CS# is Low
RAS#	CAS#	WE#	Meaning
LOW	HIGH	HIGH	Bank Activate
LOW	HIGH	LOW	Bank Precharge
HIGH	LOW	HIGH	WRITE
HIGH	LOW	LOW	READ
HIGH	HIGH	X	Power Down
LOW	LOW	HIGH	Self Refresh
HIGH	HIGH	LOW	BURST STOP
HIGH	HIGH	HIGH	NOP (Non-Operational) similar to CS# High
LOW	LOW	LOW	Mode Register Set

To access data an address must be setup before the clock by about 1 clock cycle (tAS). Then the ACTIVATE (RAS) command must be executed on an idle bank to put it in an active mode. A READ or WRITE (CAS) command is issued after the ACTIVE (RAS) command. The period between the ACTIVE command and the subsequent READ or WRITE command is the

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