Monday, February 11, 2008

PC100 SDRAM Latency

PC100 SDRAM Latency

The Clock Cycle Time:

A computer sequences its tasks based on an oscillator which is basically a clock. The faster the clock runs, the faster the tasks get done. The speed of the clock is measured by its frequency in MHz (Millions of cycles per second). Computers based on the 440BX, 440GX and 440NX PCIsets have a bus speed of 100MHz. This means the bus oscillates 100,000,000 times per second. The duration of a single oscillation is known as the Clock Cycle Time (tCK). Clock cycle times are measured in nanoseconds. 1 nanosecond (ns) = 10e-9 or 0.000000001 seconds or one billionth of a second. tCK is given by the inverse of the frequency (tCK = 1/frequency). A 100MHz oscillator gives a 10ns clock cycle time.

Therefore, the Intel PC100 Specification requires a maximum value of 10ns for tCK. A Clock Cycle Time of 8ns is currently the fastest available. 8ns modules do not necessarily perform faster than 10ns modules on a 100MHz bus. Performance is based on a number of factors that will be described below. However, 8ns modules are capable of running on a 125MHz bus and are therefore of interest to over clockers.



www.oempcworld.com

No comments: