Comparing Various ICs of PC100 SDRAM:

Comparing Various ICs of PC100 SDRAM:

Typically the suffix on the chip part number can be used to compare various modules. However, with the recent hype of PC100 SDRAM, misleading markings have appeared that have confused end users. The following tables compare various models currently marketed as PC100. Note also that according to our tests, modules with identical specifications may actually perform quite differently.

SAMSUNG

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10	NOT PC100	10ns	7 ns.	3
-GL	PC100	10 ns.	6 ns.	3
-GH	PC100	10 ns.	6 ns.	2
-8	PC100	8 ns.	6 ns.	3

TOSHIBA

Part#	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
TC59S6408BFT-10	NOT PC100	10 ns.	7 ns.	3
TC59S6408BFT-80	PC100	8 ns.	6 ns.	2

LGS

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10K	NOT PC100	10 ns.	8 ns.	3
-8	PC100	8 ns.	6 ns.	3
-7J*	PC100	10 ns.	6 ns.	3

* Note that the LG RAM -7J is a 10ns Cycle Time

MICRON

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10	NOT PC100	10 ns.	7 ns.	3
-8C	PC100	8 ns.	6 ns.	3
-8E	PC100	8 ns.	6 ns.	2

Comparing Various ICs of PC100 SDRAM:

Comparing Various ICs of PC100 SDRAM:

Typically the suffix on the chip part number can be used to compare various modules. However, with the recent hype of PC100 SDRAM, misleading markings have appeared that have confused end users. The following tables compare various models currently marketed as PC100. Note also that according to our tests, modules with identical specifications may actually perform quite differently.

SAMSUNG

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10	NOT PC100	10ns	7 ns.	3
-GL	PC100	10 ns.	6 ns.	3
-GH	PC100	10 ns.	6 ns.	2
-8	PC100	8 ns.	6 ns.	3

TOSHIBA

Part#	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
TC59S6408BFT-10	NOT PC100	10 ns.	7 ns.	3
TC59S6408BFT-80	PC100	8 ns.	6 ns.	2

LGS

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10K	NOT PC100	10 ns.	8 ns.	3
-8	PC100	8 ns.	6 ns.	3
-7J*	PC100	10 ns.	6 ns.	3

* Note that the LG RAM -7J is a 10ns Cycle Time

MICRON

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10	NOT PC100	10 ns.	7 ns.	3
-8C	PC100	8 ns.	6 ns.	3
-8E	PC100	8 ns.	6 ns.	2

Comparing Various ICs of PC100 SDRAM:

Comparing Various ICs of PC100 SDRAM:

Typically the suffix on the chip part number can be used to compare various modules. However, with the recent hype of PC100 SDRAM, misleading markings have appeared that have confused end users. The following tables compare various models currently marketed as PC100. Note also that according to our tests, modules with identical specifications may actually perform quite differently.

SAMSUNG

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10	NOT PC100	10ns	7 ns.	3
-GL	PC100	10 ns.	6 ns.	3
-GH	PC100	10 ns.	6 ns.	2
-8	PC100	8 ns.	6 ns.	3

TOSHIBA

Part#	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
TC59S6408BFT-10	NOT PC100	10 ns.	7 ns.	3
TC59S6408BFT-80	PC100	8 ns.	6 ns.	2

LGS

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10K	NOT PC100	10 ns.	8 ns.	3
-8	PC100	8 ns.	6 ns.	3
-7J*	PC100	10 ns.	6 ns.	3

* Note that the LG RAM -7J is a 10ns Cycle Time

MICRON

Part# Suffix	Performance	Clock Cycle Time (tCK)	Access Time from Clock (tAC)	CAS Latency (tCL)
-10	NOT PC100	10 ns.	7 ns.	3
-8C	PC100	8 ns.	6 ns.	3
-8E	PC100	8 ns.	6 ns.	2

Reading your register settings under Linux:

Reading your register settings under Linux:

Register values for the 440BX PCIset are listed in the 440BX Specification in section 3.3. 3.3.24 lists the values for tCL, tRCD and tRP. A 16 bit address under control register 0 (Device 0), at address offset 76h­77h defines these values. The default value is 00h. The three least significant bits are defined such that:

Bit 0:
SDRAM RAS# Precharge (tRP). This bit controls the number of DCLKs for RAS# Precharge.
0 = 3 clocks of RAS# Precharge.
1 = 2 clocks of RAS# Precharge.

Bit 1:
SDRAM RAS# to CAS# Delay (tRCD). This bit controls the number of DCLKs from a Row Activate command to a read or write command.
0 = 3 clocks will be inserted between a row activate command and either a read or write command.
1 = 2 clocks will be inserted between a row activate and either a read or write command.

Bit 2:
CAS# Latency (CL). This bit controls the number of CLKs between when a read command is sampled by the SDRAMs and when the 82443BX samples read data from the SDRAMs. If a given row is populated with a registered SDRAM DIMM, an extra clock is inserted between the read command the when the 82443BX samples read data. For a registered DIMM with CL=2, this bit should be set to 1.
0 = 3 DCLK CAS# latency.
1 = 2 DCLK CAS# latency.

If you wish to read the values of these bits you can download and run 440bx.c. Compile 440bx.c with "gcc -O -c timing timing.c." The program will dump the bit values of address offset 76h of device 0. For example, a board set to 3-2-2 would read something like:

*** 440BX SDRAM Memory Timing ***

CAS# Latency: 3 DCLKs
RAS# to CAS# Delay: 2 DCLKs
RAS# Precharge: 2 DCLKs

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CAS delay (tRCD).

CAS delay (tRCD).

Data is read out sequentially, synchronized with the positive edge of CLK. Data is sequentially bursted according to the burst mode set in the Mode Registry. The burst mode may be set to 2, 4 or 8 words or even to a full page (the entire column). The initial data from the READ command is available (data out) after a period equal to the value of the the CAS Latency (CL) as set in the Mode Registry.

Therefore the total access time to the first data word is generally equal to tAS + tRCD + CL. This may be something like 1+2+3 = 6. Subsequent data is bursted out synchronous with the clock at one clock per word for the duration of the burst mode.

As noted above the PC100 specification requires a minimum standard of 3/3/3/8. The specification also requires a 6ns or less Access Time from Clock (tAC 6ns). tAC is basically the time in nanoseconds for data to be read.

Most PC100 modules have a CL of 3. The Samsung -GH and Micron -8D and -8E have a CL of 2. Modules with a CL of 2 are difficult to produce in ample yields and are therefore much more expensive than modules with a CL of 3. The lower CL only increases total SDRAM performance marginally (~5%) and therefore are considered to offer too little bang for the buck. However, CL 2 modules are of some interest to those who over clock their systems to bus speeds of 112MHz. We do not suggest over clocking the bus speed. However, we do carry the faster modules for those who are interested in them.

The values listed in specifications may be confusing because they are alternately listed in clocks tics or nanoseconds. For example, the RAS to CAS delay, tRCD, is the number of clock cycles allowed between the ACTIVATE (RAS) command and the READ (CAS) command. The value of tRCD is generally 20ns or 30ns (2 or 3 clocks). The value of the tRCD latency in nanoseconds may be divided by the bus speed in nanoseconds (100Mhz is 10ns) and then rounded up to the nearest whole clock value. For example a tRCD of 20ns would yield a latency of 2 clocks cycles (20ns / 10ns). The RAS Precharge (tRP) is typically 20ns of 30ns. (tRP is analogous to the CAS# before RAS# (tCBR) described above for EDO RAM).

We have found that the values set in the SPD are frequently incorrect. Indeed, it is not possible to set these values correctly for all bus speeds. These values should be overridden. Lets look at CAS latency (CL) as an example. Recall That CL is the time from the READ command to the first data out. If a module is rated as 3/2/2/8 (which most are) to what value should the SPD CL be set? Suppose the module is used on a 440BX board with a 333MHz CPU. The bus speed would be 66MHz which has 15ns tCK. A 3/2/2/8 modules has a CL of 30ns. Therefore on a 66MHz bus the CL should be set to 2 (30ns/15ns) in the SPD. Suppose the same module is used on the same 440BX board with a 400MHz CPU using a 100MHz bus. The bus speed would be 100MHz which has 10ns tCK. A 3/2/2/8 modules has a CL of 30ns. Therefore on a 100MHz bus the CL should be set to 3 (30ns/10ns). To which value should this module's SPD be programmed? 2 or 3? There is no correct answer. It doesn't appear that Intel took this into account when writing the specifications of the SPD. In actual practice you'll find SPD set to very odd values indeed. Therefore, override these values in your BIOS and set them up by hand the old fashioned way. Generally you'll set these values to 3/2/2/8.

What happens if you don't set the module parameters correctly? If you set the parameters to conservatively your system may perform about 20% too slow. But no other harm will be done. If you set your module parameters too fast, you will not damage the module nor the motherboard. However, you will end up with data corruption. This corruption may be insidious and difficult to detect at first. But eventually it will catch up to you. To test for data corruption try unpacking large software packages like the entire X Windows system and running check sums. This seems to be a fairly good test for this type of data corruption.

Latency and Timing Terminology
Symbol	Name	Meaning
tCK	Clock Cycle Time	The Period of one Clock Cycle (CLK)
tCH	CLK High Level Width	The Pulse Width of CLK measured from the positive (leading) edge to the negative (trailing) edge of the wave form. (tCH = tCK - tCMS)
tCL	CLK Low Level Width	The Pulse Width of CLK measured from the negative edge to the positive edge of the wave form. (tCL = tCK + tCMH)
tAC	Access Time	DATA Access Time from Clock
CL	CAS Read Latency	READ/WRITE (CAS) Command to Data Out Period
tRCD	RAS to CAS Delay	ACTIVATE (RAS) to READ/WRITE (CAS) Command Period
tRP	RAS Precharge	PRECHARGE (RAS) to ACTIVATE (RAS) Command Period (analogous to the CAS# before RAS# (tCBR) for EDO)
tRC	RAS Cycle	Refresh/ACTIVATE to Refresh/ACTIVATE Command Period (tRC = tRAS + tRP)
tRAS	RAS Clock	ACTIVATE (RAS) to PRECHARGE (RAS) Command Period
tCCD	CAS to CAS Delay	READ/WRITE(CAS a) to READ/WRITE(CAS b) Command Period
tRRD	RAS to RAS Delay	When interleaving two banks this is the period between the ACTIVATE command of RAS Bank A and the subsequant ACTIVATE Command on RAS b. tRP is thus hidden.
tWR	WRITE	WRITE (CAS) Recovery Period
tOH	Output Data Hold	A holding period waited while valid data it output.
tHZ	Output Data High Impedance	tOH plus a residual hold time required due to impedance of the circuit.
tLZ	Output Data Low Impedance	Output Data Low Impedance Period
tDS	Data-in Setup	Data-in Setup Period
tDH	Data-in Hold	Data-in Hold Period
tAS	Address Setup	Address Setup Period
tAH	Address Hold	Address Hold Period
tCMS	Command Setup	Command Setup Period
tCMH	Command Hold	Command Hold Period
tCKS	Clock Setup	Clock Setup Period
tCKH	Clock Hold	Clock Hold Period
tREF	Refresh	Refresh Period
tRSC	Mode Register Set Cycle	Mode Register Set Cycle Period issued during startup to program CAS Latency, Addressing Mode and Burst Length

The operation of SDRAM in relation to latency:

The operation of SDRAM in relation to latency:

We have already covered topics relating to refresh and latency above. We have defined the RAS Cycle (tRC), the RAS Precharge Cycle (tRP), tRAS, AUTO REFRESH and AUTO PRECHARGE as well as the impact of continuous reads or writes versus short reads and writes on these parameters. Now we can look more closely at the process of activating a bank and reading or writing data to that bank.

As discussed previously, commands and data addresses control access to banks of data. Commands are issued by holding the voltage low or high across several leads. Four very important leads are CS#, RAS#, CAS# and WE#. When CS# is high the other three leads are ignored. When CS# is held low the voltages across RAS#, CAS# and WE# determine a set of commands used to manipulate the bank in question.

Commands issued for values of RAS#, CAS# and WE# when CS# is Low
RAS#	CAS#	WE#	Meaning
LOW	HIGH	HIGH	Bank Activate
LOW	HIGH	LOW	Bank Precharge
HIGH	LOW	HIGH	WRITE
HIGH	LOW	LOW	READ
HIGH	HIGH	X	Power Down
LOW	LOW	HIGH	Self Refresh
HIGH	HIGH	LOW	BURST STOP
HIGH	HIGH	HIGH	NOP (Non-Operational) similar to CS# High
LOW	LOW	LOW	Mode Register Set

To access data an address must be setup before the clock by about 1 clock cycle (tAS). Then the ACTIVATE (RAS) command must be executed on an idle bank to put it in an active mode. A READ or WRITE (CAS) command is issued after the ACTIVE (RAS) command. The period between the ACTIVE command and the subsequent READ or WRITE command is the

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Programming SDRAM modules with SPD EPROM's, BIOS settings and 3-2-2 notation:

Programming SDRAM modules with SPD EPROM's, BIOS settings and 3-2-2 notation:

SDRAM ICs are programmable. Values for programmable parameters are stored in the IC's Mode Registry at boot time. These values are set in a programmable register in the SDRAM IC which is set at power-up and remains set until the system is powered off. Programmable parameters include the Burst Mode, the CAS Latency (CL), the RAS Precharge Latency (tRP) and the The RAS to CAS delay (tRCD). Values for these attributes are read from the SPD EPROM on the module (See the SPD EPROM section) by the BIOS. The BIOS may use the SPD values, or the values may be overridden depending on the settings in your CMOS setup program. The final values are recorded in the 440BX registry. In a section below we document how to read these values from the 440BX registry.

In most cases these values must be overridden because the values in the SPD EPROM are incorrect. This is because the value of many parameters is dependent on bus speed. Since PC100 SDRAM may be used on boards with a 66MHz bus as well as boards with a 100MHz bus, the values stored in the SPD will frequently be set for the wrong bus speed.

In the Award BIOS you can find these settings in the "Chipset Features Setup." Change the "SDRAM Configuration" value from "By SPD" to "Disable." You can then set the respective values of "SDRAM CAS Latency," "SDRAM RAS to CAS Delay" and "SDRAM RAS Precharge" to the values of CL, tRCD and tRP respectively. In the CMOS setup these values are recorded as by values of clock tics denoted by 2T or 3T.

These three values, CL, tRCD and tRP, are often quoted with the notation 3-2-2 referring to tCL-tRCD-tRP. This should not be confused with burst timing notation as described elsewhere on this page. A value of 3-2-2 is optimal for current PC100 SDRAM on the market. 2-2-2 PC100 SDRAM has only been produced in low yields as described above. Module tolerances of 3-2-2 and 2-2-2 are most common. However, the Intel PC100 specification allows for a variety of tolerances ranging from 3-3-3 to 2-2-2.

Frequently a fourth parameter is referred to as the "DRAM Idle timer" in the BIOS. This is also known as the RAS cycle time (tRC). In the PC100 SDRAM specification this has a maximal value of 8. In an alternate notation 3-2-2 modules with a tRC of 8 are referred to as /3/2/2/8. The minimum standard for PC100 SDRAM is 3/3/3/8.

PC100 SDRAM Latency

PC100 SDRAM Latency

The Clock Cycle Time:

A computer sequences its tasks based on an oscillator which is basically a clock. The faster the clock runs, the faster the tasks get done. The speed of the clock is measured by its frequency in MHz (Millions of cycles per second). Computers based on the 440BX, 440GX and 440NX PCIsets have a bus speed of 100MHz. This means the bus oscillates 100,000,000 times per second. The duration of a single oscillation is known as the Clock Cycle Time (tCK). Clock cycle times are measured in nanoseconds. 1 nanosecond (ns) = 10e-9 or 0.000000001 seconds or one billionth of a second. tCK is given by the inverse of the frequency (tCK = 1/frequency). A 100MHz oscillator gives a 10ns clock cycle time.

Therefore, the Intel PC100 Specification requires a maximum value of 10ns for tCK. A Clock Cycle Time of 8ns is currently the fastest available. 8ns modules do not necessarily perform faster than 10ns modules on a 100MHz bus. Performance is based on a number of factors that will be described below. However, 8ns modules are capable of running on a 125MHz bus and are therefore of interest to over clockers.

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Memory Interleaving:

Memory Interleaving

The demands of new higher speed processors and parallel processing has made memory throughput (bandwidth) a bottleneck in modern computer systems. Memory interleaving is a technique implemented to increase the maximal throughput of data a memory system can provide per unit time. However, memory interleaving does not effect memory latency as discussed in the cache section.

Memory interleaving is implemented by dividing the memory system into a number independent banks which can answer read or write requests independently, in parallel. For example the Intel Orion 450GX chip set (discontinued) for the Intel Pentium Pro processor used four-way interleaved memory by dividing its memory into four banks. The most extreme interleaved design is used in current SMP vector supercomputers (Cray) which may have up to 256 way interleaved memory banks!

In a typical four-way interleaved memory system the SIMM's are divided logically into four banks. When lines of data are written to the memory four lines of data may be written simultaneously because each line can be written to each bank separately, in parallel. In contrast, in a non-interleaved system only one line may be written to memory in the same amount of time. Therefore four-way interleaved memory can read and write data four times faster than non- interleaved memory at its maximal rate. Imagine what a 256 way interleaved memory supercomputer can do! You may want to note that this technique of interleaving is analogous to disk striping in a RAID system (see our hard drive technical section) and increases through put in the same manor.

To obtain the maximal throughput of interleaved memory the data must be prefetched. Prefetch techniques are automatically utilized by pipelined and superscalar CPU's. The use of Prefetch loops is particularly important for iterative loops like "for (i=1; i<n; i++) { ... a[i] ... }." Where the CPU must Prefetch elements of a[i] from memory before they are actually called for. Problems are also encountered in matrix and vector math when an operation requires access to data in a sequence that is some multiple of the interleaving. In this cases all the data needed is in the same memory banks. However, modern compilers, especially Fortran compilers will address such issues for the programmer.

Most PC chip sets like the Intel Triton-II (430HX and 430VX) and the Intel Natoma (440FX) do not support memory interleaving because Intel does not believe PC users saturate their memory bus. However, many number crunching applications do saturate the memory bus. Increasingly Multi-processor PC's are being used for such applications and we hope to see future Intel Chip sets support memory Interleaving. We hope you send your thoughts on this to Intel. (Hint).

2K and 4K Refresh, Columns and Rows

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2K and 4K Refresh, Columns and Rows:

The Joint Electronics Design Engineering Council (JEDEC) has two approved refresh types for 16Mb ICs called 2K and 4K. In rare cases modules with 1K refresh are encountered. The performance of 1K, 2K and 4K ICs is similar in most cases, but the newer 4K 16Mb ICs use less energy. 4K ICs conserve about 20mA of energy under worst-case conditions because they require fewer columns. However, 4K designs have a half the page depth of 2K devices.

Common Types of EDO and FPM Chips
Size (MB)	Size (Mb)	Configuration	Refresh	tREF	Banks	Pins
512KB	4Mb	1Mx4	1K	16ms	1	4 sets of 5 pins SOJ
2MB	16Mb	4Mx4	2K or 4K	16ms	1	4 sets of 6 pins SOJ or TSOP
		2Mx8	2K	32ms		4 sets of 7 pins SOJ or TSOP
		1Mx16	1K	64ms		50-pin SOJ or TSOP
8MB	64Mb	16Mx4	4K or 8K	64ms	1	4 sets of 8 SOJ or TSOP II
		8Mx8	4K or 8K	64ms		4 sets of 8 SOJ or TSOP II
		4Mx16	4K	64ms		50-pin TSOP II

16Mb EDO ICs typically implement 2K technology:
Traditional 2K technology is implemented on most older 16Mb EDO RAM chips. In the 4Mx4 scheme bits of data are stored in a large array with 2,048 (2Kb) columns and 2,048 (2Kb) rows. Each bit in this array is uniquely identified by a pair of values called the column-address bit and a row-address bit. To address 2,048 columns there must be 11 column-address bits ( 2^11 = 2,048). Likewise there must be 11 row-address bits. Thus each bit is identified by a unique pair or coordinates (column-address_bit_value, row-address_bit_value). This allows for addressing of all 4,194,304 bits (2,048^2) or 4Mbs. These bits are generally denoted as A0-AXX where XX is the last bit.

A term called the page depth is used to denote the number of columns in a chip. Thus a chip with a 2K refresh has a 2K page depth. The cycle refresh is a term used to refer to the number of rows. Thus a chip with a 2K refresh has a 2K cycle refresh.

Our description of this array has only two dimensions so far; columns and rows. In the final IC four such arrays are stacked in a 3 dimensional data structure. A set of arrays are stacked like cards in a deck. The number of arrays in the stack is generally 4, 8 or 16. For this example four arrays will be used. We say that this data structure is four bits wide. The total number of bits in a chip then is 16,777,216 (4,194,304 bits per 2D array x 4 arrays). Thus each chip can store 16Mbs or 4MBs of data. Eight such chips are used in a 16MB module (8 x 16Mb chips = 16MB module) and 16 are used in 32MB modules (16 x 16Mb chips = 32MB module).

Periodically the charge stored in each bit must be refreshed or the charge will decay and the value of the bit of data will be lost. DRAM (Dynamic Random Access Memory) is really just a bunch of capacitors that can store energy in an array of bits. The array of bits can be accessed randomly. However, the capacitors can only store this energy for a short time before it discharges it. Therefore DRAM must be refreshed (re-energizing of the capacitors) every 15.6µs (a microsecond equals 10^-6 seconds) per row. Each time the capacitors are refreshed the memory is re-written. For this reason DRAM is also called volatile memory.

Using the RAS-ONLY refresh (ROR) method, the refresh is done is a systematic manner, each column is refreshed row by row in sequence. In a typical EDO module each row takes 15.6µs to refresh. Therefore in a 2K module the refresh time per column would be 15.6µs x 2048 rows = 32ms (1 millisecond equals 10^-6 seconds). This value is called the tREF. It refers to the refresh interval of the entire array.

In some 16Mb ICs a 4K refresh scheme is utilized where the number of columns has been decreased. To decrease the number of columns and keep the total number of bits the same in the array, the number of rows must be increased. In this scheme bits of data are stored in a large array with 1Kb (1,024) columns and 4Kb (4,096) rows. To address 1,024 columns there must be 10 column-address bits ( 2^10 = 1,024). Likewise there must be 12 row-address bits ( 2^12 = 4,096).

Thus a chip with a 4K refresh has a page depth (number of columns) of 1K and a 4K cycle refresh (number of rows).

64Mb EDO ICs typically implement 4K technology:
In 64MB and 128MB modules 64Mb chips are used. Like 16Mb EDO ICs, 16MX4 64Mb chips are based on a three dimensional array. However in 16MX4 chips a common configuration features 4,096 columns by 4,096 rows by 4 bits. This yields 67,108,864 bits or 64Mbs or 8MBs per chip.

64Mb EDO ICs use CBR:
In 64Mb ICs, the ROR method would require a 7.8µs per row refresh interval with an 8K refresh device using the ROR method. Instead in 64Mb EDO ICs an internal double-row refresh is implemented with CAS-BEFORE-RAS (CBR) cycles. Using this method a 15.6µs per row refresh interval can be maintained with 8K rows. Future 256Mb chips promise 7.8µs or even a 3.9µs per row refresh rates.

Types of SDRAM Chips
Size (MB)	Size (Mb)	Configuration	Banks	Config per Bank	Pins
2MB	16Mb	4Mx4, 2Mx8	2	2Mx4, 1Mx8	44-pin TSOP
8MB	64Mb	16Mx4, 8Mx8, 16Mx4	4	4Mx4, 2Mx8, 1Mx16	54-pin TSOP
16MB	128Mb	32Mx4, 16Mx8, 8Mx16	4	8Mx4, 4Mx8, 2Mx16	54-pin TSOP
32MB	256Mb	N/A	N/A	N/A	N/A
128MB	1Gb	N/A	N/A	N/A	N/A

64Mb and 128Mb SDRAM ICs are typical implementations of 4K technology using four banks:
In 64Mb ICs four 3D arrays may be organized into four separate banks (quad-bank). Each bank is addressed by the values of a pair of bank bits. These are usually denoted BS0 and BS1. Banks may be interleaved as discussed in the next section. A bank typically stores 16,777,216 bits. The total number of bits in a chip then is 67,108,864 (16,777,216 bits per bank x 4 banks). Thus each chip can store 64Mbs or 8MBs of data. Eight such chips are used in a 64MB module and 16 are used in 128MB modules.

A 64Mb 4K chip may be organized in a variety of ways. A typical module will have four banks. Each bank in turn may include a 4Mb array that is 4 bits wide. The 4Mb array will have 4K rows and 1K columns. Such a chip would be called a 16Mx4. Note that the 16M refers to the 4Mb array times four banks, while the x4 refers to the number of bits per bank.

Alternately a bank may have a 2Mb array that is 8 bits wide. The 2Mb array will have 4K rows and 512 columns. Such a module would be called a 8Mx8. The 8M refers to the 2Mb array times four banks. The x8 refers to the number of bits per bank.

Finally a bank may have a 1Mb array that is 16 bits wide. The 1Mb array will have 4K rows and 256 columns. Such a chip would be called a 4Mx16. The 4M refers to the 1Mb array by four banks. The x16 refers to the number of bits per bank.

In a typical SDRAM module each row takes 15.6µs (1 microsecond equals 10^-9 seconds) to refresh. Therefore in a 4K module the refresh time per column would be 15.6µs x 4096 rows = 64ms (1 millisecond equals 10^-6 seconds). Thus a 4K module typically has a tREF of 64ms.

Refresh periods are alternated with periods in which the data can be accessed in a cycle called the RAS Cycle (tRC). The RAS Cycle has two periods. The first period is the called the tRAS. During tRAS a bank my be marked as ACTIVE. After being marked as ACTIVE the data in this bank can be extracted or written with a READ or WRITE command. After the data if any is out, the bank then enters a RAS Precharge Cycle (tRP). During tRP the bits are refreshed. The refresh can be executed automatically after a READ or WRITE command saving time if AUTO REFRESH or AUTO PRECHARGE is enabled. The Latency of tRP is frequently masked by Memory Interleaving of banks as described in the next section. In this case one bank is in Active mode (tRAS) while an alternate bank is in refresh mode (tRP). These banks may alternate or several banks may alternate so that the effects of tRP is insignificant to the total data output on the bus. tRP is has the least significant effect when long reads or writes are conducted. It can have a critical impact with short reads or writes where row changes are common such as in the case of matrix math. In this case SDRAM tRP timings become critical.

Refresh Terminology
Symbol	Name	Meaning
tRP	RAS Precharge	PRECHARGE (RAS) to ACTIVATE (RAS) Command Period (analogous to the CAS# before RAS# (tCBR) for EDO)
tRC	RAS Cycle	Refresh/ACTIVATE to Refresh/ACTIVATE Command Period (tRC = tRAS + tRP)
tRAS	RAS Clock	ACTIVATE (RAS) to PRECHARGE (RAS) Command Period
tREF	Refresh	Refresh Period

The meaning of SIMM, DIMM and the number of pins

The meaning of SIMM, DIMM and the number of pins :

Your processor communicates to the memory and add on cards through a set of parallel channels in a bus. The number it bits in the bus is merely the number of channels present. For example, motherboards using the Triton-II (430HX) and the Natoma (440FX) have a 64 bit memory bus (connecting the processor to the cache and the cache to the memory) and a 32-bit PCI bus (connecting to the add on cards). The wider the bus (i.e. the more bits) the more data that can travel per cycle thus the faster the data transfer. The data transfer rate is the width of the bus in bits times the number of transfers per second in megahertz times the data size. However, if you have a 64-bit bus you must access your memory 64- bits at a time. Each SIMM is only 32-bits wide so you must install them in pairs to get the full 64-bits. Then two SIMM's are accessed as one logical bank of RAM. Older boards that accept a single SIMM are have only a 32-bit memory bus and this reduces speed by half. There is also a small advantage to using two banks or four SIMM's of the same size.

SIMM's connect to the motherboard bus via 72 Gold or Tin (Palladium Nickel) leads. Indeed SIMM's are called Single In-line Memory Modules because that have 72 pins in a single row of in- line leads. Older SIMM's had 30-pins. Other Memory modules such as DIMM (Dual In-line Memory Modules) have all 64-bits (on 128-pins) in one set of leads so you only need to install one DIMM per bank.

Nearly 99% of motherboards use Tin (Palladium Nickel) which can plate onto the noble Gold of SIMM's in a cathode-anode reaction. According to semi- conductor corrosion specialists the amount of corrosion possible can not effect the proper function of the SIMM's because of the small contact surface. If it was true the finest SIMM makers like NEC would stop production of GOLD SIMM's immediately. Indeed, Tin is a little harder to work with because it tarnishes faster. Most engineers who design SIMM's agree that gold is the best. Only Intel has claimed otherwise. Indeed, no such cases of corrosion have been reported.

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Buffered RAM and Voltage

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Buffered RAM and Voltage :

Recently larger 64MB and 128MB SIMM's and DIMM's have been introduced. These modules frequently stack multiple chips (loads) in what is known as a composite architecture (See the Composite section of this page). This increases the total load on the memory bus in the form of increased capacitance. This is a bad thing. If you recall, a capacitor in a DC circuit will charge like a battery when a voltage is applied across it and it will discharge a current when the voltage is removed. If a pulse of voltage is sent through a circuit with a capacitance its signal will rise slowly and decay slowly. Capacitance in a circuit adds a delay in response Signals, such as memory address lines, are sent encoded as a series of voltage pulses. Therefore, an increased capacitance has the effect of slowing the overall rate at which signals may be conducted. The ability of the motherboard to overcome this effect is know as the load driving capacity of the board. This is generally not sufficient to drive larger modules with higher capacitance. Rather than redesign the motherboard and increase its load driving capacity, the industry has opted to modify the memory module by adding a line driver (buffer) such as an 74F244. This is a single chip on the memory module which is much smaller than a normal RAM chip. You can identify buffered modules by looking for this chip. The line driver handles all loading of the RAM chips and redirects all incoming and outgoing signals. It introduces some delay but this is more than offset by the increase in signal rise and fall times. So the net effect is to increase the speed of memory access. In practical terms, using a line driver (buffer) is more important when you install more than one bank of very high density SIMM's or DIMM's.

An alternate method of dealing with the issue of increased capacitance is to merely lower the voltage of the signal sent to the memory module. It takes less time for a signal to rise and fall if the voltage is lower. If the voltage has to be increased from 0 to 5v to send a signal across a capacitor it will take a long time for the capacitor to charge and decay. Likewise if the signal it sent to a memory module with a higher capacitance it will take a long time for the signal to rise and fall. If the pulse is merely from 0 to 3.3v than it will take much less time for the signal to rise and fall. Therefore lowering the voltage of the memory module from 5v to 3.3v has the effect of speeding up the system just like the case of adding a memory buffer. You can even combine lower voltage and a buffer to augment signal speed.

Older SIMM's use 5 volt technology. Newer DIMM's are available in both 3.3v and 5v formats. Some "mixed-mode" modules are actually 3.3v modules that can run at 5v. Many 3.3v DIMM's can actually run at 5v and therefore can be mixed with 5v DIMM's but in practice it is not a good idea to mix 3.3v DIMM's with 5v SIMM or DIMM's unless your absolutely sure about the manufacturer's IC specifications. On newer motherboards that use both 5v SIMM's and DIMM's it is a good idea to use 5v DIMM's if you plan to use the SIMM socket. If you don't plan to use SIMM's at all you can use all 3.3v DIMM's. The choice of voltage you use is not dependent on the motherboard chip set.

Bits and Bytes

Bits and Bytes:

Remember that one bit represents one switch that is either on or off and there are eight bits to one byte. That means that one byte can store two to the eighth power or 256 different numbers i.e. a binary number with eight digits can range from 0 to 255 and thus can store any one of 256 values. (Each of these values can be a assigned a character such as a letter or a number or a punctuation mark. In this way one byte can store any one of 256 different characters. On modern computers this is called the ASCII character set. So when you think of a byte think of one letter). Also remember that a set of 1024 bytes is called a kilobyte (KB) and 1024 kilobytes is called a megabyte (MB). Also 1024 bits is called a kilobit (Kb) and 1024 kilobits is called a megabit (Mb).

RAM

RAM :

When you pick up a SIMM you'll see a number of chips on either side of a flat board. These chips are called DRAM (Dynamic Random Access Memory). On non-parity SIMM's you'll find eight DRAM chips on one or both sides of the SIMM depending on the size:

A 4MB SIMM has 8 DRAM chips on one side.

An 8MB SIMM has 16 DRAM chips with 8 DRAM chips on each side.

A 16MB SIMM has 8 DRAM chips on one side.

A 32MB SIMM has 16 DRAM chips with 8 DRAM chips on each side.

Both 4MB and 16MB SIMM's look alike because they have 8 chips on one side. Likewise 8MB and 32MB SIMM's look alike because they have 8 chips on each side for a total of 16 chips. You can tell them apart by looking at the DRAM chips themselves.

Each DRAM chip is either 512KB's (1Mx4's ), 2MB's (4Mx4's) or 8MB's (16Mx4). 1Mx4's are used on 4MB and 8MB SIMM's. 4Mx4's are used on 16MB and 32MB SIMM's. 16Mx4's are used in 64MB and 128MB chips. 1Mx4's chips have four sets of five pins and 4Mx4's have four sets of six pins. So for example, you can tell an 8MB SIMM from a 32MB SIMM by counting the pins. The 8MB SIMM will have four sets of 5 pins on each of its chip while the 32MB SIMM will have 6 pins.

16Mx4's are available in a variety of configurations, the most common is a 54-pin TSOP package. 16Mx4's are used in 64MB and 128MB modules. Later this year 32MB (256Mb) chips will be available allowing for 256MB and 512MB modules. By 2001 128MB (1Gb) chips will be available in 1GB and 2GB modules. http://www.oempcworld.com/