2K and 4K Refresh, Columns and Rows

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2K and 4K Refresh, Columns and Rows:

The Joint Electronics Design Engineering Council (JEDEC) has two approved refresh types for 16Mb ICs called 2K and 4K. In rare cases modules with 1K refresh are encountered. The performance of 1K, 2K and 4K ICs is similar in most cases, but the newer 4K 16Mb ICs use less energy. 4K ICs conserve about 20mA of energy under worst-case conditions because they require fewer columns. However, 4K designs have a half the page depth of 2K devices.

Common Types of EDO and FPM Chips
Size (MB)	Size (Mb)	Configuration	Refresh	tREF	Banks	Pins
512KB	4Mb	1Mx4	1K	16ms	1	4 sets of 5 pins SOJ
2MB	16Mb	4Mx4	2K or 4K	16ms	1	4 sets of 6 pins SOJ or TSOP
		2Mx8	2K	32ms		4 sets of 7 pins SOJ or TSOP
		1Mx16	1K	64ms		50-pin SOJ or TSOP
8MB	64Mb	16Mx4	4K or 8K	64ms	1	4 sets of 8 SOJ or TSOP II
		8Mx8	4K or 8K	64ms		4 sets of 8 SOJ or TSOP II
		4Mx16	4K	64ms		50-pin TSOP II

16Mb EDO ICs typically implement 2K technology:
Traditional 2K technology is implemented on most older 16Mb EDO RAM chips. In the 4Mx4 scheme bits of data are stored in a large array with 2,048 (2Kb) columns and 2,048 (2Kb) rows. Each bit in this array is uniquely identified by a pair of values called the column-address bit and a row-address bit. To address 2,048 columns there must be 11 column-address bits ( 2^11 = 2,048). Likewise there must be 11 row-address bits. Thus each bit is identified by a unique pair or coordinates (column-address_bit_value, row-address_bit_value). This allows for addressing of all 4,194,304 bits (2,048^2) or 4Mbs. These bits are generally denoted as A0-AXX where XX is the last bit.

A term called the page depth is used to denote the number of columns in a chip. Thus a chip with a 2K refresh has a 2K page depth. The cycle refresh is a term used to refer to the number of rows. Thus a chip with a 2K refresh has a 2K cycle refresh.

Our description of this array has only two dimensions so far; columns and rows. In the final IC four such arrays are stacked in a 3 dimensional data structure. A set of arrays are stacked like cards in a deck. The number of arrays in the stack is generally 4, 8 or 16. For this example four arrays will be used. We say that this data structure is four bits wide. The total number of bits in a chip then is 16,777,216 (4,194,304 bits per 2D array x 4 arrays). Thus each chip can store 16Mbs or 4MBs of data. Eight such chips are used in a 16MB module (8 x 16Mb chips = 16MB module) and 16 are used in 32MB modules (16 x 16Mb chips = 32MB module).

Periodically the charge stored in each bit must be refreshed or the charge will decay and the value of the bit of data will be lost. DRAM (Dynamic Random Access Memory) is really just a bunch of capacitors that can store energy in an array of bits. The array of bits can be accessed randomly. However, the capacitors can only store this energy for a short time before it discharges it. Therefore DRAM must be refreshed (re-energizing of the capacitors) every 15.6µs (a microsecond equals 10^-6 seconds) per row. Each time the capacitors are refreshed the memory is re-written. For this reason DRAM is also called volatile memory.

Using the RAS-ONLY refresh (ROR) method, the refresh is done is a systematic manner, each column is refreshed row by row in sequence. In a typical EDO module each row takes 15.6µs to refresh. Therefore in a 2K module the refresh time per column would be 15.6µs x 2048 rows = 32ms (1 millisecond equals 10^-6 seconds). This value is called the tREF. It refers to the refresh interval of the entire array.

In some 16Mb ICs a 4K refresh scheme is utilized where the number of columns has been decreased. To decrease the number of columns and keep the total number of bits the same in the array, the number of rows must be increased. In this scheme bits of data are stored in a large array with 1Kb (1,024) columns and 4Kb (4,096) rows. To address 1,024 columns there must be 10 column-address bits ( 2^10 = 1,024). Likewise there must be 12 row-address bits ( 2^12 = 4,096).

Thus a chip with a 4K refresh has a page depth (number of columns) of 1K and a 4K cycle refresh (number of rows).

64Mb EDO ICs typically implement 4K technology:
In 64MB and 128MB modules 64Mb chips are used. Like 16Mb EDO ICs, 16MX4 64Mb chips are based on a three dimensional array. However in 16MX4 chips a common configuration features 4,096 columns by 4,096 rows by 4 bits. This yields 67,108,864 bits or 64Mbs or 8MBs per chip.

64Mb EDO ICs use CBR:
In 64Mb ICs, the ROR method would require a 7.8µs per row refresh interval with an 8K refresh device using the ROR method. Instead in 64Mb EDO ICs an internal double-row refresh is implemented with CAS-BEFORE-RAS (CBR) cycles. Using this method a 15.6µs per row refresh interval can be maintained with 8K rows. Future 256Mb chips promise 7.8µs or even a 3.9µs per row refresh rates.

Types of SDRAM Chips
Size (MB)	Size (Mb)	Configuration	Banks	Config per Bank	Pins
2MB	16Mb	4Mx4, 2Mx8	2	2Mx4, 1Mx8	44-pin TSOP
8MB	64Mb	16Mx4, 8Mx8, 16Mx4	4	4Mx4, 2Mx8, 1Mx16	54-pin TSOP
16MB	128Mb	32Mx4, 16Mx8, 8Mx16	4	8Mx4, 4Mx8, 2Mx16	54-pin TSOP
32MB	256Mb	N/A	N/A	N/A	N/A
128MB	1Gb	N/A	N/A	N/A	N/A

64Mb and 128Mb SDRAM ICs are typical implementations of 4K technology using four banks:
In 64Mb ICs four 3D arrays may be organized into four separate banks (quad-bank). Each bank is addressed by the values of a pair of bank bits. These are usually denoted BS0 and BS1. Banks may be interleaved as discussed in the next section. A bank typically stores 16,777,216 bits. The total number of bits in a chip then is 67,108,864 (16,777,216 bits per bank x 4 banks). Thus each chip can store 64Mbs or 8MBs of data. Eight such chips are used in a 64MB module and 16 are used in 128MB modules.

A 64Mb 4K chip may be organized in a variety of ways. A typical module will have four banks. Each bank in turn may include a 4Mb array that is 4 bits wide. The 4Mb array will have 4K rows and 1K columns. Such a chip would be called a 16Mx4. Note that the 16M refers to the 4Mb array times four banks, while the x4 refers to the number of bits per bank.

Alternately a bank may have a 2Mb array that is 8 bits wide. The 2Mb array will have 4K rows and 512 columns. Such a module would be called a 8Mx8. The 8M refers to the 2Mb array times four banks. The x8 refers to the number of bits per bank.

Finally a bank may have a 1Mb array that is 16 bits wide. The 1Mb array will have 4K rows and 256 columns. Such a chip would be called a 4Mx16. The 4M refers to the 1Mb array by four banks. The x16 refers to the number of bits per bank.

In a typical SDRAM module each row takes 15.6µs (1 microsecond equals 10^-9 seconds) to refresh. Therefore in a 4K module the refresh time per column would be 15.6µs x 4096 rows = 64ms (1 millisecond equals 10^-6 seconds). Thus a 4K module typically has a tREF of 64ms.

Refresh periods are alternated with periods in which the data can be accessed in a cycle called the RAS Cycle (tRC). The RAS Cycle has two periods. The first period is the called the tRAS. During tRAS a bank my be marked as ACTIVE. After being marked as ACTIVE the data in this bank can be extracted or written with a READ or WRITE command. After the data if any is out, the bank then enters a RAS Precharge Cycle (tRP). During tRP the bits are refreshed. The refresh can be executed automatically after a READ or WRITE command saving time if AUTO REFRESH or AUTO PRECHARGE is enabled. The Latency of tRP is frequently masked by Memory Interleaving of banks as described in the next section. In this case one bank is in Active mode (tRAS) while an alternate bank is in refresh mode (tRP). These banks may alternate or several banks may alternate so that the effects of tRP is insignificant to the total data output on the bus. tRP is has the least significant effect when long reads or writes are conducted. It can have a critical impact with short reads or writes where row changes are common such as in the case of matrix math. In this case SDRAM tRP timings become critical.

Refresh Terminology
Symbol	Name	Meaning
tRP	RAS Precharge	PRECHARGE (RAS) to ACTIVATE (RAS) Command Period (analogous to the CAS# before RAS# (tCBR) for EDO)
tRC	RAS Cycle	Refresh/ACTIVATE to Refresh/ACTIVATE Command Period (tRC = tRAS + tRP)
tRAS	RAS Clock	ACTIVATE (RAS) to PRECHARGE (RAS) Command Period
tREF	Refresh	Refresh Period