CAS delay (tRCD).

CAS delay (tRCD).

Data is read out sequentially, synchronized with the positive edge of CLK. Data is sequentially bursted according to the burst mode set in the Mode Registry. The burst mode may be set to 2, 4 or 8 words or even to a full page (the entire column). The initial data from the READ command is available (data out) after a period equal to the value of the the CAS Latency (CL) as set in the Mode Registry.

Therefore the total access time to the first data word is generally equal to tAS + tRCD + CL. This may be something like 1+2+3 = 6. Subsequent data is bursted out synchronous with the clock at one clock per word for the duration of the burst mode.

As noted above the PC100 specification requires a minimum standard of 3/3/3/8. The specification also requires a 6ns or less Access Time from Clock (tAC 6ns). tAC is basically the time in nanoseconds for data to be read.

Most PC100 modules have a CL of 3. The Samsung -GH and Micron -8D and -8E have a CL of 2. Modules with a CL of 2 are difficult to produce in ample yields and are therefore much more expensive than modules with a CL of 3. The lower CL only increases total SDRAM performance marginally (~5%) and therefore are considered to offer too little bang for the buck. However, CL 2 modules are of some interest to those who over clock their systems to bus speeds of 112MHz. We do not suggest over clocking the bus speed. However, we do carry the faster modules for those who are interested in them.

The values listed in specifications may be confusing because they are alternately listed in clocks tics or nanoseconds. For example, the RAS to CAS delay, tRCD, is the number of clock cycles allowed between the ACTIVATE (RAS) command and the READ (CAS) command. The value of tRCD is generally 20ns or 30ns (2 or 3 clocks). The value of the tRCD latency in nanoseconds may be divided by the bus speed in nanoseconds (100Mhz is 10ns) and then rounded up to the nearest whole clock value. For example a tRCD of 20ns would yield a latency of 2 clocks cycles (20ns / 10ns). The RAS Precharge (tRP) is typically 20ns of 30ns. (tRP is analogous to the CAS# before RAS# (tCBR) described above for EDO RAM).

We have found that the values set in the SPD are frequently incorrect. Indeed, it is not possible to set these values correctly for all bus speeds. These values should be overridden. Lets look at CAS latency (CL) as an example. Recall That CL is the time from the READ command to the first data out. If a module is rated as 3/2/2/8 (which most are) to what value should the SPD CL be set? Suppose the module is used on a 440BX board with a 333MHz CPU. The bus speed would be 66MHz which has 15ns tCK. A 3/2/2/8 modules has a CL of 30ns. Therefore on a 66MHz bus the CL should be set to 2 (30ns/15ns) in the SPD. Suppose the same module is used on the same 440BX board with a 400MHz CPU using a 100MHz bus. The bus speed would be 100MHz which has 10ns tCK. A 3/2/2/8 modules has a CL of 30ns. Therefore on a 100MHz bus the CL should be set to 3 (30ns/10ns). To which value should this module's SPD be programmed? 2 or 3? There is no correct answer. It doesn't appear that Intel took this into account when writing the specifications of the SPD. In actual practice you'll find SPD set to very odd values indeed. Therefore, override these values in your BIOS and set them up by hand the old fashioned way. Generally you'll set these values to 3/2/2/8.

What happens if you don't set the module parameters correctly? If you set the parameters to conservatively your system may perform about 20% too slow. But no other harm will be done. If you set your module parameters too fast, you will not damage the module nor the motherboard. However, you will end up with data corruption. This corruption may be insidious and difficult to detect at first. But eventually it will catch up to you. To test for data corruption try unpacking large software packages like the entire X Windows system and running check sums. This seems to be a fairly good test for this type of data corruption.

Latency and Timing Terminology
Symbol	Name	Meaning
tCK	Clock Cycle Time	The Period of one Clock Cycle (CLK)
tCH	CLK High Level Width	The Pulse Width of CLK measured from the positive (leading) edge to the negative (trailing) edge of the wave form. (tCH = tCK - tCMS)
tCL	CLK Low Level Width	The Pulse Width of CLK measured from the negative edge to the positive edge of the wave form. (tCL = tCK + tCMH)
tAC	Access Time	DATA Access Time from Clock
CL	CAS Read Latency	READ/WRITE (CAS) Command to Data Out Period
tRCD	RAS to CAS Delay	ACTIVATE (RAS) to READ/WRITE (CAS) Command Period
tRP	RAS Precharge	PRECHARGE (RAS) to ACTIVATE (RAS) Command Period (analogous to the CAS# before RAS# (tCBR) for EDO)
tRC	RAS Cycle	Refresh/ACTIVATE to Refresh/ACTIVATE Command Period (tRC = tRAS + tRP)
tRAS	RAS Clock	ACTIVATE (RAS) to PRECHARGE (RAS) Command Period
tCCD	CAS to CAS Delay	READ/WRITE(CAS a) to READ/WRITE(CAS b) Command Period
tRRD	RAS to RAS Delay	When interleaving two banks this is the period between the ACTIVATE command of RAS Bank A and the subsequant ACTIVATE Command on RAS b. tRP is thus hidden.
tWR	WRITE	WRITE (CAS) Recovery Period
tOH	Output Data Hold	A holding period waited while valid data it output.
tHZ	Output Data High Impedance	tOH plus a residual hold time required due to impedance of the circuit.
tLZ	Output Data Low Impedance	Output Data Low Impedance Period
tDS	Data-in Setup	Data-in Setup Period
tDH	Data-in Hold	Data-in Hold Period
tAS	Address Setup	Address Setup Period
tAH	Address Hold	Address Hold Period
tCMS	Command Setup	Command Setup Period
tCMH	Command Hold	Command Hold Period
tCKS	Clock Setup	Clock Setup Period
tCKH	Clock Hold	Clock Hold Period
tREF	Refresh	Refresh Period
tRSC	Mode Register Set Cycle	Mode Register Set Cycle Period issued during startup to program CAS Latency, Addressing Mode and Burst Length